This invention relates to phase locked loop (PLL) systems in which the density of data transitions in the data signal varies.
Monolithic PLL circuits have become the basic building blocks of many consumer and industrial electronic systems. In telecommunication data systems, for example, the PLL is an integral part of the clock recovery subsystem. The PLL may be used to recover the clock signal from the data signal; the recovered clock may then be used, for example, to regenerate the data signal.
The basic PLL system generally comprises three elements; (1) a phase detector, (2) a loop filter, and (3) a voltage controlled oscillator (VCO), which are interconnected in a feedback system as shown in FIG. 12.1 of "Bipolar and MOS Analog Integrated Circuit Design," A. B. Grebene, John Wiley & Sons (1984). The phase detector compares the phase of an input signal V.sub.s with the phase of the VCO and generates a control voltage V.sub.d. This voltage V.sub.d is filtered by the loop filter, the output of which is applied to the control terminal of the VCO to control its frequency of oscillation.
The loop gain, K.sub.L, of the PLL is defined as follows: EQU K.sub.L =K.sub.D K.sub.o ( 1)
where K.sub.D (V/rad) is the phase detector conversion gain, and K.sub.o (Hz/V) is the voltage-to-frequency conversion gain of the VCO.
It is well known that the phase detector gain K.sub.D, and hence the loop gain, of a clock recovery PLL is dependent on the transition density of the data signal. (D. L. Duttweiler, BSTJ, Vol. 55, No. 1 (1976)). That is, when the data signal undergoes few data transitions, the phase detector has periods of time when no data transitions occur to compare with the VCO recovered clock. The effective phase detector gain K.sub.DD is then degraded by a factor D&lt;1 defined as EQU D=f.sub.trans /f.sub.clk ( 2) EQU and EQU K.sub.DD =K.sub.D D (3)
where f.sub.trans is the frequency of the data transitions and f.sub.clk is the frequency of the recovered clock.
Consider two cases illustrated by FIGS. 1 and 2. In both cases the PLL is locked to an input data signal, but the clock signal is lagging the data signal by a phase error .DELTA.. In FIG. 1, there is only one rising clock cycle transition between adjacent data transitions; thus, the degrading factor D=1. But, in FIG. 2, there are three rising clock cycle transitions between adjacent data transitions; thus D=1/3. Therefore, there are three times the number of error corrections in the D=1 case than in the D=1/3 case. This difference effectively makes the phase detector gain of FIG. 2, K.sub.D2 =1/3 K.sub.D1, where K.sub.D1 is the phase detector gain of FIG. 1, even though the phase detectors themselves have physically the same implementation.
This data-dependent variation of the phase detector gain will cause variations in the PLL closed loop dynamics and may be undesirable. For example, in a second order active loop filter PLL (Grebene, supra, FIG. 12.9), the natural frequency, the damping factor and the 3 dB frequency all decrease as K.sub.DD decreases, but the jitter peaking increases. This effect is particularly troublesome in systems in which the PLLs (or repeaters which include the PLLs) are cascaded. For example, in token ring systems data may be inserted/extracted at different nodes such that different repeaters/PLLs see different data streams. With prior art PLLs, the transfer function of the PLL shifts with transition density such that some PLLs may lose lock; others may not.